ZAMIEŚĆ OFERTĘ PRACY
Zamieść
|
Primary role responsibilities will include:
- The role will involve working with the system architect to define module level architectures and documenting these module specifications
- Converting the architecture into RTL while considering constraints such as area, speed, power and performance
- Verification of the RTL at module level and top level in conjunction with the simulator group
- Synthesis and formal verification
- Power and performance analysis
- Liaising with other teams such as simulation, drivers, research and other hardware teams
- Mentoring and supervising more junior engineers
Required Skills:
- An excellent knowledge of digital design techniques, including high speed and low power design.
- You must be proficient in RTL design with previous experience coding in VHDL or verilog.
- You must be familiar with the whole ASIC design process and have a clear understanding of SOC architecture.
- Previous experience with synthesis, formal verification and power compiler is highly desirable.
- Experience working in video is highly desirable.
Desirable Skills:
- Video experience or knowledge
- Scripting: Perl, TCL, make and cshell
- Familiar with unix/linux working environment
- Familiar with emulator and FPGA systems
